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b8ca67b114
Vendor msm-5.x kernels declared duplicate indices for some of display nodes to be used by separate display RSC and BCM voters. As it is not clear how this separate BCM should be modelled upstream and the device trees do not use these indices, drop them for now. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240804-sm8350-fixes-v1-6-1149dd8399fe@linaro.org Signed-off-by: Georgi Djakov <djakov@kernel.org>
163 lines
4.3 KiB
C
163 lines
4.3 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Qualcomm SM8350 interconnect IDs
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*
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* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
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* Copyright (c) 2021, Linaro Limited
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*/
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#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_SM8350_H
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#define __DT_BINDINGS_INTERCONNECT_QCOM_SM8350_H
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#define MASTER_QSPI_0 0
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#define MASTER_QUP_1 1
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#define MASTER_A1NOC_CFG 2
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#define MASTER_SDCC_4 3
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#define MASTER_UFS_MEM 4
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#define MASTER_USB3_0 5
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#define MASTER_USB3_1 6
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#define SLAVE_A1NOC_SNOC 7
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#define SLAVE_SERVICE_A1NOC 8
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#define MASTER_QDSS_BAM 0
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#define MASTER_QUP_0 1
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#define MASTER_QUP_2 2
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#define MASTER_A2NOC_CFG 3
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#define MASTER_CRYPTO 4
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#define MASTER_IPA 5
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#define MASTER_PCIE_0 6
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#define MASTER_PCIE_1 7
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#define MASTER_QDSS_ETR 8
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#define MASTER_SDCC_2 9
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#define MASTER_UFS_CARD 10
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#define SLAVE_A2NOC_SNOC 11
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#define SLAVE_ANOC_PCIE_GEM_NOC 12
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#define SLAVE_SERVICE_A2NOC 13
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#define MASTER_GEM_NOC_CNOC 0
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#define MASTER_GEM_NOC_PCIE_SNOC 1
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#define MASTER_QDSS_DAP 2
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#define SLAVE_AHB2PHY_SOUTH 3
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#define SLAVE_AHB2PHY_NORTH 4
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#define SLAVE_AOSS 5
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#define SLAVE_APPSS 6
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#define SLAVE_CAMERA_CFG 7
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#define SLAVE_CLK_CTL 8
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#define SLAVE_CDSP_CFG 9
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#define SLAVE_RBCPR_CX_CFG 10
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#define SLAVE_RBCPR_MMCX_CFG 11
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#define SLAVE_RBCPR_MX_CFG 12
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#define SLAVE_CRYPTO_0_CFG 13
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#define SLAVE_CX_RDPM 14
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#define SLAVE_DCC_CFG 15
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#define SLAVE_DISPLAY_CFG 16
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#define SLAVE_GFX3D_CFG 17
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#define SLAVE_HWKM 18
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#define SLAVE_IMEM_CFG 19
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#define SLAVE_IPA_CFG 20
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#define SLAVE_IPC_ROUTER_CFG 21
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#define SLAVE_LPASS 22
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#define SLAVE_CNOC_MSS 23
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#define SLAVE_MX_RDPM 24
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#define SLAVE_PCIE_0_CFG 25
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#define SLAVE_PCIE_1_CFG 26
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#define SLAVE_PDM 27
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#define SLAVE_PIMEM_CFG 28
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#define SLAVE_PKA_WRAPPER_CFG 29
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#define SLAVE_PMU_WRAPPER_CFG 30
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#define SLAVE_QDSS_CFG 31
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#define SLAVE_QSPI_0 32
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#define SLAVE_QUP_0 33
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#define SLAVE_QUP_1 34
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#define SLAVE_QUP_2 35
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#define SLAVE_SDCC_2 36
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#define SLAVE_SDCC_4 37
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#define SLAVE_SECURITY 38
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#define SLAVE_SPSS_CFG 39
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#define SLAVE_TCSR 40
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#define SLAVE_TLMM 41
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#define SLAVE_UFS_CARD_CFG 42
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#define SLAVE_UFS_MEM_CFG 43
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#define SLAVE_USB3_0 44
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#define SLAVE_USB3_1 45
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#define SLAVE_VENUS_CFG 46
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#define SLAVE_VSENSE_CTRL_CFG 47
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#define SLAVE_A1NOC_CFG 48
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#define SLAVE_A2NOC_CFG 49
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#define SLAVE_DDRSS_CFG 50
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#define SLAVE_CNOC_MNOC_CFG 51
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#define SLAVE_SNOC_CFG 52
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#define SLAVE_BOOT_IMEM 53
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#define SLAVE_IMEM 54
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#define SLAVE_PIMEM 55
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#define SLAVE_SERVICE_CNOC 56
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#define SLAVE_PCIE_0 57
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#define SLAVE_PCIE_1 58
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#define SLAVE_QDSS_STM 59
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#define SLAVE_TCU 60
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#define MASTER_CNOC_DC_NOC 0
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#define SLAVE_LLCC_CFG 1
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#define SLAVE_GEM_NOC_CFG 2
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#define MASTER_GPU_TCU 0
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#define MASTER_SYS_TCU 1
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#define MASTER_APPSS_PROC 2
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#define MASTER_COMPUTE_NOC 3
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#define MASTER_GEM_NOC_CFG 4
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#define MASTER_GFX3D 5
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#define MASTER_MNOC_HF_MEM_NOC 6
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#define MASTER_MNOC_SF_MEM_NOC 7
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#define MASTER_ANOC_PCIE_GEM_NOC 8
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#define MASTER_SNOC_GC_MEM_NOC 9
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#define MASTER_SNOC_SF_MEM_NOC 10
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#define SLAVE_MSS_PROC_MS_MPU_CFG 11
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#define SLAVE_MCDMA_MS_MPU_CFG 12
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#define SLAVE_GEM_NOC_CNOC 13
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#define SLAVE_LLCC 14
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#define SLAVE_MEM_NOC_PCIE_SNOC 15
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#define SLAVE_SERVICE_GEM_NOC_1 16
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#define SLAVE_SERVICE_GEM_NOC_2 17
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#define SLAVE_SERVICE_GEM_NOC 18
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#define MASTER_CNOC_LPASS_AG_NOC 0
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#define SLAVE_LPASS_CORE_CFG 1
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#define SLAVE_LPASS_LPI_CFG 2
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#define SLAVE_LPASS_MPU_CFG 3
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#define SLAVE_LPASS_TOP_CFG 4
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#define SLAVE_SERVICES_LPASS_AML_NOC 5
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#define SLAVE_SERVICE_LPASS_AG_NOC 6
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#define MASTER_LLCC 0
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#define SLAVE_EBI1 1
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#define MASTER_CAMNOC_HF 0
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#define MASTER_CAMNOC_ICP 1
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#define MASTER_CAMNOC_SF 2
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#define MASTER_CNOC_MNOC_CFG 3
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#define MASTER_VIDEO_P0 4
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#define MASTER_VIDEO_P1 5
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#define MASTER_VIDEO_PROC 6
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#define MASTER_MDP0 7
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#define MASTER_MDP1 8
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#define MASTER_ROTATOR 9
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#define SLAVE_MNOC_HF_MEM_NOC 10
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#define SLAVE_MNOC_SF_MEM_NOC 11
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#define SLAVE_SERVICE_MNOC 12
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#define MASTER_CDSP_NOC_CFG 0
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#define MASTER_CDSP_PROC 1
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#define SLAVE_CDSP_MEM_NOC 2
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#define SLAVE_SERVICE_NSP_NOC 3
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#define MASTER_A1NOC_SNOC 0
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#define MASTER_A2NOC_SNOC 1
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#define MASTER_SNOC_CFG 2
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#define MASTER_PIMEM 3
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#define MASTER_GIC 4
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#define SLAVE_SNOC_GEM_NOC_GC 5
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#define SLAVE_SNOC_GEM_NOC_SF 6
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#define SLAVE_SERVICE_SNOC 7
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#endif
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