mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2024-12-29 17:23:36 +00:00
b472b996a4
Modify license to include dual licensing as GPL-2.0-only OR MIT license for TI specific phy header files. This allows for Linux kernel files to be used in other Operating System ecosystems such as Zephyr or FreeBSD. While at this, update the GPL-2.0 to be GPL-2.0-only to be in sync with latest SPDX conventions (GPL-2.0 is deprecated). While at this, update the TI copyright year to sync with current year to indicate license change. Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Trent Piepho <tpiepho@impinj.com> Cc: Wadim Egorov <w.egorov@phytec.de> Cc: Kip Broadhurst <kbroadhurst@ti.com> Signed-off-by: Udit Kumar <u-kumar1@ti.com> Acked-by: Wadim Egorov <w.egorov@phytec.de> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
43 lines
1.4 KiB
C
43 lines
1.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
|
|
/*
|
|
* Device Tree constants for the Texas Instruments DP83869 PHY
|
|
*
|
|
* Author: Dan Murphy <dmurphy@ti.com>
|
|
*
|
|
* Copyright (C) 2015-2024 Texas Instruments Incorporated - https://www.ti.com/
|
|
*/
|
|
|
|
#ifndef _DT_BINDINGS_TI_DP83869_H
|
|
#define _DT_BINDINGS_TI_DP83869_H
|
|
|
|
/* PHY CTRL bits */
|
|
#define DP83869_PHYCR_FIFO_DEPTH_3_B_NIB 0x00
|
|
#define DP83869_PHYCR_FIFO_DEPTH_4_B_NIB 0x01
|
|
#define DP83869_PHYCR_FIFO_DEPTH_6_B_NIB 0x02
|
|
#define DP83869_PHYCR_FIFO_DEPTH_8_B_NIB 0x03
|
|
|
|
/* IO_MUX_CFG - Clock output selection */
|
|
#define DP83869_CLK_O_SEL_CHN_A_RCLK 0x0
|
|
#define DP83869_CLK_O_SEL_CHN_B_RCLK 0x1
|
|
#define DP83869_CLK_O_SEL_CHN_C_RCLK 0x2
|
|
#define DP83869_CLK_O_SEL_CHN_D_RCLK 0x3
|
|
#define DP83869_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4
|
|
#define DP83869_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5
|
|
#define DP83869_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6
|
|
#define DP83869_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7
|
|
#define DP83869_CLK_O_SEL_CHN_A_TCLK 0x8
|
|
#define DP83869_CLK_O_SEL_CHN_B_TCLK 0x9
|
|
#define DP83869_CLK_O_SEL_CHN_C_TCLK 0xa
|
|
#define DP83869_CLK_O_SEL_CHN_D_TCLK 0xb
|
|
#define DP83869_CLK_O_SEL_REF_CLK 0xc
|
|
|
|
#define DP83869_RGMII_COPPER_ETHERNET 0x00
|
|
#define DP83869_RGMII_1000_BASE 0x01
|
|
#define DP83869_RGMII_100_BASE 0x02
|
|
#define DP83869_RGMII_SGMII_BRIDGE 0x03
|
|
#define DP83869_1000M_MEDIA_CONVERT 0x04
|
|
#define DP83869_100M_MEDIA_CONVERT 0x05
|
|
#define DP83869_SGMII_COPPER_ETHERNET 0x06
|
|
|
|
#endif
|