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be3e224ec5
Fix thermal zone names for consistency with the other SoCs:
- GPU0 must be used as the first GPU item.
- SOCx deal with audio DSP, video, and infra subsystems.
The naming must be fixed "atomically" so compilation does not break.
As a result, the change is made in the dt-bindings and in the LVTS
driver within a single commit, despite the checkpatch warning.
The definitions can be safely modified here because they are used only
in the LVTS driver, which is modified accordingly, and have not yet
been included in a released kernel.
Fixes: 78c88534e5e1 ("dt-bindings: thermal: mediatek: Add LVTS thermal controller definition for MT8188")
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Julien Panis <jpanis@baylibre.com>
Link: https://lore.kernel.org/r/20240603-mtk-thermal-mt818x-dtsi-v7-2-8c8e3c7a3643@baylibre.com
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
84 lines
2.1 KiB
C
84 lines
2.1 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2023 MediaTek Inc.
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* Author: Balsam CHIHI <bchihi@baylibre.com>
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*/
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#ifndef __MEDIATEK_LVTS_DT_H
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#define __MEDIATEK_LVTS_DT_H
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#define MT7988_CPU_0 0
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#define MT7988_CPU_1 1
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#define MT7988_ETH2P5G_0 2
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#define MT7988_ETH2P5G_1 3
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#define MT7988_TOPS_0 4
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#define MT7988_TOPS_1 5
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#define MT7988_ETHWARP_0 6
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#define MT7988_ETHWARP_1 7
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#define MT8186_LITTLE_CPU0 0
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#define MT8186_LITTLE_CPU1 1
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#define MT8186_LITTLE_CPU2 2
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#define MT8186_CAM 3
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#define MT8186_BIG_CPU0 4
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#define MT8186_BIG_CPU1 5
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#define MT8186_NNA 6
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#define MT8186_ADSP 7
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#define MT8186_GPU 8
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#define MT8188_MCU_LITTLE_CPU0 0
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#define MT8188_MCU_LITTLE_CPU1 1
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#define MT8188_MCU_LITTLE_CPU2 2
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#define MT8188_MCU_LITTLE_CPU3 3
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#define MT8188_MCU_BIG_CPU0 4
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#define MT8188_MCU_BIG_CPU1 5
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#define MT8188_AP_APU 0
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#define MT8188_AP_GPU0 1
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#define MT8188_AP_GPU1 2
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#define MT8188_AP_ADSP 3
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#define MT8188_AP_VDO 4
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#define MT8188_AP_INFRA 5
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#define MT8188_AP_CAM1 6
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#define MT8188_AP_CAM2 7
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#define MT8195_MCU_BIG_CPU0 0
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#define MT8195_MCU_BIG_CPU1 1
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#define MT8195_MCU_BIG_CPU2 2
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#define MT8195_MCU_BIG_CPU3 3
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#define MT8195_MCU_LITTLE_CPU0 4
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#define MT8195_MCU_LITTLE_CPU1 5
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#define MT8195_MCU_LITTLE_CPU2 6
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#define MT8195_MCU_LITTLE_CPU3 7
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#define MT8195_AP_VPU0 8
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#define MT8195_AP_VPU1 9
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#define MT8195_AP_GPU0 10
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#define MT8195_AP_GPU1 11
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#define MT8195_AP_VDEC 12
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#define MT8195_AP_IMG 13
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#define MT8195_AP_INFRA 14
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#define MT8195_AP_CAM0 15
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#define MT8195_AP_CAM1 16
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#define MT8192_MCU_BIG_CPU0 0
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#define MT8192_MCU_BIG_CPU1 1
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#define MT8192_MCU_BIG_CPU2 2
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#define MT8192_MCU_BIG_CPU3 3
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#define MT8192_MCU_LITTLE_CPU0 4
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#define MT8192_MCU_LITTLE_CPU1 5
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#define MT8192_MCU_LITTLE_CPU2 6
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#define MT8192_MCU_LITTLE_CPU3 7
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#define MT8192_AP_VPU0 8
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#define MT8192_AP_VPU1 9
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#define MT8192_AP_GPU0 10
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#define MT8192_AP_GPU1 11
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#define MT8192_AP_INFRA 12
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#define MT8192_AP_CAM 13
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#define MT8192_AP_MD0 14
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#define MT8192_AP_MD1 15
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#define MT8192_AP_MD2 16
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#endif /* __MEDIATEK_LVTS_DT_H */
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