linux/include/dt-bindings/clock/mediatek,mt6735-infracfg.h
Yassine Oudjana ea1cca0268 dt-bindings: clock: Add MediaTek MT6735 clock and reset bindings
Add clock definitions for the main clock and reset controllers of MT6735
(apmixedsys, topckgen, infracfg and pericfg).

Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241017071708.38663-2-y.oudjana@protonmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-10-17 12:24:35 -07:00

26 lines
672 B
C

/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
#ifndef _DT_BINDINGS_CLK_MT6735_INFRACFG_H
#define _DT_BINDINGS_CLK_MT6735_INFRACFG_H
#define CLK_INFRA_DBG 0
#define CLK_INFRA_GCE 1
#define CLK_INFRA_TRBG 2
#define CLK_INFRA_CPUM 3
#define CLK_INFRA_DEVAPC 4
#define CLK_INFRA_AUDIO 5
#define CLK_INFRA_GCPU 6
#define CLK_INFRA_L2C_SRAM 7
#define CLK_INFRA_M4U 8
#define CLK_INFRA_CLDMA 9
#define CLK_INFRA_CONNMCU_BUS 10
#define CLK_INFRA_KP 11
#define CLK_INFRA_APXGPT 12
#define CLK_INFRA_SEJ 13
#define CLK_INFRA_CCIF0_AP 14
#define CLK_INFRA_CCIF1_AP 15
#define CLK_INFRA_PMIC_SPI 16
#define CLK_INFRA_PMIC_WRAP 17
#endif