David Ung 0e766c2d9f clk: tegra: PLLD2 fixes for hdmi
Set correct pll_d2_out0 divider and correct the p div values for pll_d2.

Signed-off-by: David Ung <davidu@nvidia.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
2014-02-17 16:18:11 +02:00
..
2014-02-14 16:13:00 -08:00
2014-02-17 16:18:11 +02:00
2014-02-14 10:40:47 +01:00
2014-01-29 20:00:13 -08:00
2014-02-14 12:48:16 -08:00
2014-01-25 13:19:10 -08:00
2014-02-14 16:13:00 -08:00
2014-01-26 11:00:41 -08:00
2014-02-14 10:33:45 -08:00
2014-02-14 10:32:28 -08:00
2014-01-15 14:51:22 -08:00
2014-01-27 08:15:51 -08:00
2014-02-14 16:14:11 -08:00
2014-02-13 11:12:00 -08:00
2014-01-22 22:24:35 -08:00
2014-02-12 12:28:05 -08:00