James Liao 196de71a9d clk: mediatek: Fix calculation of PLL rate settings ...

Avoid u32 overflow when calculate post divider setting, and
increase the max post divider setting from 3 (/8) to 4 (/16).

Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

2015-07-28 11:58:54 -07:00

..

clk-gate.c

clk: mediatek: Initialize clk_init_data

2015-05-19 18:40:48 -07:00

clk-gate.h

clk: mediatek: Add initial common clock support for Mediatek SoCs.

2015-05-05 22:50:31 -07:00

clk-mt8135.c

clk: mediatek: Fix apmixedsys clock registration

2015-06-04 14:07:07 -07:00

clk-mt8173.c

clk: mediatek: mt8173: Fix enabling of critical clocks

2015-07-06 15:54:13 -07:00

clk-mtk.c

clk: mediatek: Add initial common clock support for Mediatek SoCs.

2015-05-05 22:50:31 -07:00

clk-mtk.h

clk: mediatek: Add reset controller support

2015-05-05 22:50:33 -07:00

clk-pll.c

clk: mediatek: Fix calculation of PLL rate settings

2015-07-28 11:58:54 -07:00

Makefile

clk: mediatek: Add basic clocks for Mediatek MT8173.

2015-05-05 22:50:38 -07:00

reset.c

clk: mediatek: Add reset controller support

2015-05-05 22:50:33 -07:00