Russ Anderson 1f3b6045f7 [IA64] Disable/re-enable CPE interrupts on Altix
When the CPE handler encounters too many CPEs (such as a solid single
bit memory error), it sets up a polling timer and disables the CPE
interrupt (to avoid excessive overhead logging the stream of single
bit errors).  disable_irq_nosync() calls chip->disable() to provide
a chipset specifiec interface for disabling the interrupt.  This patch
adds the Altix specific support to disable and re-enable the CPE interrupt.

Signed-off-by: Russ Anderson (rja@sgi.com)
Signed-off-by: Tony Luck <tony.luck@intel.com>
2007-11-06 15:40:31 -08:00
..
2007-05-11 05:38:25 -04:00
2005-04-16 15:20:36 -07:00
2007-07-19 13:48:00 -07:00
2007-05-10 09:35:30 -07:00
2006-06-21 11:19:22 -07:00
2006-06-21 11:19:22 -07:00
2005-04-16 15:20:36 -07:00
2007-10-29 10:54:33 -07:00
2007-07-09 13:37:44 -07:00
2007-07-25 13:08:26 -07:00
2007-07-29 17:09:29 -07:00
2007-05-11 14:55:43 -07:00
2006-12-12 12:00:55 -08:00
2007-10-16 09:43:10 -07:00
2007-10-17 14:28:38 -07:00
2007-05-11 14:55:43 -07:00
2007-05-11 14:55:43 -07:00
2005-04-16 15:20:36 -07:00
2005-04-16 15:20:36 -07:00
2006-12-07 10:48:19 -08:00
2007-05-11 14:55:43 -07:00
2005-04-16 15:20:36 -07:00
2007-05-08 14:51:59 -07:00
2005-04-16 15:20:36 -07:00
2005-04-16 15:20:36 -07:00
2007-06-26 13:33:10 -07:00