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201ddc0577
A proper clock driver for ralink SoCs has been added. This driver is also a reset provider for the SoC. Hence there is no need to have reset related code in 'arch/mips/ralink' folder anymore. The only code that remains is the one related with mips_reboot_setup where a PCI reset is performed. We maintain this because I cannot test old ralink board with PCI to be sure all works if we remove also this code. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> |
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.. | ||
bootrom.c | ||
cevt-rt3352.c | ||
clk.c | ||
common.h | ||
early_printk.c | ||
ill_acc.c | ||
irq-gic.c | ||
irq.c | ||
Kconfig | ||
Makefile | ||
mt7620.c | ||
mt7621.c | ||
of.c | ||
Platform | ||
prom.c | ||
reset.c | ||
rt288x.c | ||
rt305x.c | ||
rt3883.c | ||
timer-gic.c | ||
timer.c |