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413d5e09ca
At the late production stages new dev ids were introduced. These are
now in production, so its important for the driver to recognize these.
And also fix the board caps for AQC115C adapter.
Fixes: b3f0c79cba206 ("net: atlantic: A2 hw_ops skeleton")
Signed-off-by: Nikita Danilov <ndanilov@aquantia.com>
Signed-off-by: Sudarsana Reddy Kalluru <skalluru@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
78 lines
2.1 KiB
C
78 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Atlantic Network Driver
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*
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* Copyright (C) 2014-2019 aQuantia Corporation
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* Copyright (C) 2019-2020 Marvell International Ltd.
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*/
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/* File aq_common.h: Basic includes for all files in project. */
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#ifndef AQ_COMMON_H
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#define AQ_COMMON_H
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#include <linux/etherdevice.h>
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#include <linux/pci.h>
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#include <linux/if_vlan.h>
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#include "aq_cfg.h"
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#include "aq_utils.h"
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#define PCI_VENDOR_ID_AQUANTIA 0x1D6A
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#define AQ_DEVICE_ID_0001 0x0001
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#define AQ_DEVICE_ID_D100 0xD100
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#define AQ_DEVICE_ID_D107 0xD107
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#define AQ_DEVICE_ID_D108 0xD108
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#define AQ_DEVICE_ID_D109 0xD109
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#define AQ_DEVICE_ID_AQC100 0x00B1
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#define AQ_DEVICE_ID_AQC107 0x07B1
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#define AQ_DEVICE_ID_AQC108 0x08B1
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#define AQ_DEVICE_ID_AQC109 0x09B1
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#define AQ_DEVICE_ID_AQC111 0x11B1
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#define AQ_DEVICE_ID_AQC112 0x12B1
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#define AQ_DEVICE_ID_AQC100S 0x80B1
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#define AQ_DEVICE_ID_AQC107S 0x87B1
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#define AQ_DEVICE_ID_AQC108S 0x88B1
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#define AQ_DEVICE_ID_AQC109S 0x89B1
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#define AQ_DEVICE_ID_AQC111S 0x91B1
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#define AQ_DEVICE_ID_AQC112S 0x92B1
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#define AQ_DEVICE_ID_AQC113DEV 0x00C0
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#define AQ_DEVICE_ID_AQC113CS 0x94C0
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#define AQ_DEVICE_ID_AQC113CA 0x34C0
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#define AQ_DEVICE_ID_AQC114CS 0x93C0
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#define AQ_DEVICE_ID_AQC113 0x04C0
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#define AQ_DEVICE_ID_AQC113C 0x14C0
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#define AQ_DEVICE_ID_AQC115C 0x12C0
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#define AQ_DEVICE_ID_AQC116C 0x11C0
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#define HW_ATL_NIC_NAME "Marvell (aQuantia) AQtion 10Gbit Network Adapter"
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#define AQ_HWREV_ANY 0
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#define AQ_HWREV_1 1
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#define AQ_HWREV_2 2
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#define AQ_NIC_RATE_10G BIT(0)
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#define AQ_NIC_RATE_5G BIT(1)
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#define AQ_NIC_RATE_2G5 BIT(2)
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#define AQ_NIC_RATE_1G BIT(3)
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#define AQ_NIC_RATE_100M BIT(4)
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#define AQ_NIC_RATE_10M BIT(5)
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#define AQ_NIC_RATE_1G_HALF BIT(6)
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#define AQ_NIC_RATE_100M_HALF BIT(7)
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#define AQ_NIC_RATE_10M_HALF BIT(8)
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#define AQ_NIC_RATE_EEE_10G BIT(9)
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#define AQ_NIC_RATE_EEE_5G BIT(10)
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#define AQ_NIC_RATE_EEE_2G5 BIT(11)
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#define AQ_NIC_RATE_EEE_1G BIT(12)
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#define AQ_NIC_RATE_EEE_100M BIT(13)
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#define AQ_NIC_RATE_EEE_MSK (AQ_NIC_RATE_EEE_10G |\
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AQ_NIC_RATE_EEE_5G |\
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AQ_NIC_RATE_EEE_2G5 |\
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AQ_NIC_RATE_EEE_1G |\
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AQ_NIC_RATE_EEE_100M)
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#endif /* AQ_COMMON_H */
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