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3759ec678e
The DTPM framework is available but without a way to configure it. This change provides a way to create a hierarchy of DTPM node where the power consumption reflects the sum of the children's power consumption. It is up to the platform to specify an array of dtpm nodes where each element has a pointer to its parent, except the top most one. The type of the node gives the indication of which initialization callback to call. At this time, we can create a virtual node, where its purpose is to be a parent in the hierarchy, and a DT node where the name describes its path. In order to ensure a nice self-encapsulation, the DTPM subsys array contains a couple of initialization functions, one to setup the DTPM backend and one to initialize it up. With this approach, the DTPM framework has a very few material to export. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Link: https://lore.kernel.org/r/20220128163537.212248-3-daniel.lezcano@linaro.org
61 lines
1.9 KiB
Plaintext
61 lines
1.9 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
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#
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# Generic power capping sysfs interface configuration
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#
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menuconfig POWERCAP
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bool "Generic powercap sysfs driver"
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help
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The power capping sysfs interface allows kernel subsystems to expose power
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capping settings to user space in a consistent way. Usually, it consists
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of multiple control types that determine which settings may be exposed and
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power zones representing parts of the system that can be subject to power
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capping.
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If you want this code to be compiled in, say Y here.
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if POWERCAP
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# Client driver configurations go here.
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config INTEL_RAPL_CORE
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tristate
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config INTEL_RAPL
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tristate "Intel RAPL Support via MSR Interface"
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depends on X86 && IOSF_MBI
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select INTEL_RAPL_CORE
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help
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This enables support for the Intel Running Average Power Limit (RAPL)
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technology via MSR interface, which allows power limits to be enforced
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and monitored on modern Intel processors (Sandy Bridge and later).
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In RAPL, the platform level settings are divided into domains for
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fine grained control. These domains include processor package, DRAM
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controller, CPU core (Power Plane 0), graphics uncore (Power Plane
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1), etc.
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config IDLE_INJECT
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bool "Idle injection framework"
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depends on CPU_IDLE
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default n
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help
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This enables support for the idle injection framework. It
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provides a way to force idle periods on a set of specified
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CPUs for power capping. Idle period can be injected
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synchronously on a set of specified CPUs or alternatively
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on a per CPU basis.
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config DTPM
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bool "Power capping for Dynamic Thermal Power Management (EXPERIMENTAL)"
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depends on OF
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help
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This enables support for the power capping for the dynamic
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thermal power management userspace engine.
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config DTPM_CPU
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bool "Add CPU power capping based on the energy model"
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depends on DTPM && ENERGY_MODEL
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help
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This enables support for CPU power limitation based on
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energy model.
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endif
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