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a26f067fea
Changes since v8: - Corrected license identifiers Changes since v7: - Add padding to struct rogue_fwif_ccb_ctl to place read and write offsets in different cache lines Changes since v5: - Split up header commit due to size - Add BRN 71242 to device info Changes since v4: - Add FW header device info Signed-off-by: Sarah Walker <sarah.walker@imgtec.com> Signed-off-by: Donald Robson <donald.robson@imgtec.com> Acked-by: Maxime Ripard <mripard@kernel.org> Link: https://lore.kernel.org/r/aa681533a02bd2d46af17a6a6010f4d6048fbb0a.1700668843.git.donald.robson@imgtec.com Signed-off-by: Maxime Ripard <mripard@kernel.org>
61 lines
1.9 KiB
C
61 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
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/* Copyright (c) 2023 Imagination Technologies Ltd. */
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#ifndef PVR_ROGUE_FWIF_COMMON_H
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#define PVR_ROGUE_FWIF_COMMON_H
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#include <linux/build_bug.h>
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/*
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* This macro represents a mask of LSBs that must be zero on data structure
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* sizes and offsets to ensure they are 8-byte granular on types shared between
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* the FW and host driver.
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*/
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#define PVR_FW_ALIGNMENT_LSB 7U
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/* Macro to test structure size alignment. */
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#define PVR_FW_STRUCT_SIZE_ASSERT(_a) \
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static_assert((sizeof(_a) & PVR_FW_ALIGNMENT_LSB) == 0U, \
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"Size of " #_a " is not properly aligned")
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/* The master definition for data masters known to the firmware. */
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#define PVR_FWIF_DM_GP (0)
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/* Either TDM or 2D DM is present. */
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/* When the 'tla' feature is present in the hw (as per @pvr_device_features). */
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#define PVR_FWIF_DM_2D (1)
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/*
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* When the 'fastrender_dm' feature is present in the hw (as per
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* @pvr_device_features).
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*/
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#define PVR_FWIF_DM_TDM (1)
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#define PVR_FWIF_DM_GEOM (2)
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#define PVR_FWIF_DM_FRAG (3)
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#define PVR_FWIF_DM_CDM (4)
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#define PVR_FWIF_DM_RAY (5)
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#define PVR_FWIF_DM_GEOM2 (6)
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#define PVR_FWIF_DM_GEOM3 (7)
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#define PVR_FWIF_DM_GEOM4 (8)
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#define PVR_FWIF_DM_LAST PVR_FWIF_DM_GEOM4
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/* Maximum number of DM in use: GP, 2D/TDM, GEOM, 3D, CDM, RAY, GEOM2, GEOM3, GEOM4 */
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#define PVR_FWIF_DM_MAX (PVR_FWIF_DM_LAST + 1U)
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/* GPU Utilisation states */
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#define PVR_FWIF_GPU_UTIL_STATE_IDLE 0U
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#define PVR_FWIF_GPU_UTIL_STATE_ACTIVE 1U
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#define PVR_FWIF_GPU_UTIL_STATE_BLOCKED 2U
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#define PVR_FWIF_GPU_UTIL_STATE_NUM 3U
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#define PVR_FWIF_GPU_UTIL_STATE_MASK 0x3ULL
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/*
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* Maximum amount of register writes that can be done by the register
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* programmer (FW or META DMA). This is not a HW limitation, it is only
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* a protection against malformed inputs to the register programmer.
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*/
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#define PVR_MAX_NUM_REGISTER_PROGRAMMER_WRITES 128U
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#endif /* PVR_ROGUE_FWIF_COMMON_H */
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