Bartosz Wawrzyniak 2d0f973b5f phy: cadence: Sierra: Fix offset of DEQ open eye algorithm control register ...

Fix the value of SIERRA_DEQ_OPENEYE_CTRL_PREG and add a definition for
SIERRA_DEQ_TAU_EPIOFFSET_MODE_PREG. This fixes the SGMII single link
register configuration.

Fixes: 7a5ad9b4b98c ("phy: cadence: Sierra: Update single link PCIe register configuration")
Signed-off-by: Bartosz Wawrzyniak <bwawrzyn@cisco.com>
Link: https://lore.kernel.org/r/20241003123405.1101157-1-bwawrzyn@cisco.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

2024-10-07 11:55:34 +05:30

..

cdns-dphy-rx.c

phy: Explicitly include correct DT includes

2023-07-17 11:52:56 +05:30

cdns-dphy.c

phy: Explicitly include correct DT includes

2023-07-17 11:52:56 +05:30

Kconfig

phy: cadence: Add Cadence D-PHY Rx driver

2022-03-02 19:54:42 +05:30

Makefile

phy: cadence: Add Cadence D-PHY Rx driver

2022-03-02 19:54:42 +05:30

phy-cadence-salvo.c

phy: cadence: salvo: Add cdns,usb2-disconnect-threshold-microvolt property

2023-05-19 23:14:06 +05:30

phy-cadence-sierra.c

phy: cadence: Sierra: Fix offset of DEQ open eye algorithm control register

2024-10-07 11:55:34 +05:30

phy-cadence-torrent.c

phy: cadence-torrent: add support for three or more links using 2 protocols

2024-08-05 21:28:50 +05:30