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Reset controllers and clock controllers are combined into one IP block on Qualcomm chipsets. Usually a reset signal is associated with each clock branch but sometimes a reset signal is associated with a handful of clocks. Either way the register interface is the same; set a bit to assert a reset and clear a bit to deassert a reset. Add support for these types of resets signals. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
9 lines
338 B
Makefile
9 lines
338 B
Makefile
obj-$(CONFIG_COMMON_CLK_QCOM) += clk-qcom.o
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clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-regmap.o
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clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-pll.o
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clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-rcg.o
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clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-rcg2.o
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clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += clk-branch.o
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clk-qcom-$(CONFIG_COMMON_CLK_QCOM) += reset.o
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