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958ba5c239
Convert the Calxeda clock bindings to DT schema format using json-schema. This just covers the actual PLL and divider clock nodes. In the actual DTs they are somewhat unconnected (no ranges or bus compatible) children of the sregs node, but for the actual clock bindings this is not relevant. One oddity is that the addresses are relative to the parent node, without that being pronounced using a ranges property. But this is too late to fix now. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org>
83 lines
1.9 KiB
YAML
83 lines
1.9 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/calxeda.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Device Tree Clock bindings for Calxeda highbank platform
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description: |
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This binding covers the Calxeda SoC internal peripheral and bus clocks
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as used by peripherals. The clocks live inside the "system register"
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region of the SoC, so are typically presented as children of an
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"hb-sregs" node.
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maintainers:
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- Andre Przywara <andre.przywara@arm.com>
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properties:
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"#clock-cells":
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const: 0
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compatible:
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enum:
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- calxeda,hb-pll-clock
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- calxeda,hb-a9periph-clock
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- calxeda,hb-a9bus-clock
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- calxeda,hb-emmc-clock
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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required:
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- "#clock-cells"
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- compatible
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- clocks
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- reg
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additionalProperties: false
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examples:
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- |
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sregs@3fffc000 {
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compatible = "calxeda,hb-sregs";
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reg = <0x3fffc000 0x1000>;
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clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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osc: oscillator {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <33333000>;
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};
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ddrpll: ddrpll@108 {
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#clock-cells = <0>;
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compatible = "calxeda,hb-pll-clock";
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clocks = <&osc>;
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reg = <0x108>;
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};
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a9pll: a9pll@100 {
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#clock-cells = <0>;
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compatible = "calxeda,hb-pll-clock";
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clocks = <&osc>;
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reg = <0x100>;
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};
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a9periphclk: a9periphclk@104 {
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#clock-cells = <0>;
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compatible = "calxeda,hb-a9periph-clock";
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clocks = <&a9pll>;
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reg = <0x104>;
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};
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};
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};
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...
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