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fba5618451
The examples template is a 'simple-bus' with a size of 1 cell for had between 2 and 4 cells which really only errors on I2C or SPI type devices with a single cell. The easiest fix in most cases is to change the 'reg' property to for 1 cell address and size. In some cases with child devices having 2 cells, that doesn't make sense so a bus node is needed. Acked-by: Stephen Boyd <sboyd@kernel.org> # clk Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Rob Herring <robh@kernel.org>
77 lines
1.6 KiB
YAML
77 lines
1.6 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/bitmain,bm1880-clk.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Bitmain BM1880 Clock Controller
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maintainers:
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- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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description: |
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The Bitmain BM1880 clock controller generates and supplies clock to
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various peripherals within the SoC.
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This binding uses common clock bindings
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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properties:
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compatible:
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const: bitmain,bm1880-clk
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reg:
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items:
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- description: pll registers
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- description: system registers
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reg-names:
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items:
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- const: pll
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- const: sys
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clocks:
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maxItems: 1
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clock-names:
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const: osc
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'#clock-cells':
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const: 1
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required:
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- compatible
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- reg
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- reg-names
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- clocks
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- clock-names
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- '#clock-cells'
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additionalProperties: false
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examples:
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# Clock controller node:
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- |
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clk: clock-controller@e8 {
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compatible = "bitmain,bm1880-clk";
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reg = <0xe8 0x0c>, <0x800 0xb0>;
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reg-names = "pll", "sys";
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clocks = <&osc>;
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clock-names = "osc";
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#clock-cells = <1>;
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};
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# Example UART controller node that consumes clock generated by the clock controller:
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- |
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uart0: serial@58018000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x58018000 0x2000>;
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clocks = <&clk 45>, <&clk 46>;
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clock-names = "baudclk", "apb_pclk";
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interrupts = <0 9 4>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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...
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