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edfcc455c8
The chipidea controller doesn't fully support sglist, such as it can not transfer data spanned more dTDs to form a bus packet, so it can only work on very limited cases. The limitations as below: 1. the end address of the first sg buffer must be 4KB aligned. 2. the start and end address of the middle sg buffer must be 4KB aligned. 3. the start address of the first sg buffer must be 4KB aligned. However, not all the use cases violate these limitations. To make the controller compatible with most of the cases, this will try to bounce the problem sglist entries which can be found by sglist_get_invalid_entry(). Then a bounced line buffer (the size will roundup to page size) will be allocated to replace the remaining problem sg entries. The data will be copied between problem sg entries and bounce buffer according to the transfer direction. The bounce buffer will be freed when the request completed. Acked-by: Peter Chen <peter.chen@kernel.com> Signed-off-by: Xu Yang <xu.yang_2@nxp.com> Link: https://lore.kernel.org/r/20240923081203.2851768-3-xu.yang_2@nxp.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
101 lines
2.4 KiB
C
101 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* udc.h - ChipIdea UDC structures
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*
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* Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
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*
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* Author: David Lopo
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*/
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#ifndef __DRIVERS_USB_CHIPIDEA_UDC_H
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#define __DRIVERS_USB_CHIPIDEA_UDC_H
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#include <linux/list.h>
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#define CTRL_PAYLOAD_MAX 64
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#define RX 0 /* similar to USB_DIR_OUT but can be used as an index */
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#define TX 1 /* similar to USB_DIR_IN but can be used as an index */
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/* DMA layout of transfer descriptors */
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struct ci_hw_td {
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/* 0 */
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__le32 next;
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#define TD_TERMINATE BIT(0)
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#define TD_ADDR_MASK (0xFFFFFFEUL << 5)
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/* 1 */
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__le32 token;
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#define TD_STATUS (0x00FFUL << 0)
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#define TD_STATUS_TR_ERR BIT(3)
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#define TD_STATUS_DT_ERR BIT(5)
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#define TD_STATUS_HALTED BIT(6)
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#define TD_STATUS_ACTIVE BIT(7)
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#define TD_MULTO (0x0003UL << 10)
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#define TD_IOC BIT(15)
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#define TD_TOTAL_BYTES (0x7FFFUL << 16)
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/* 2 */
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__le32 page[5];
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#define TD_CURR_OFFSET (0x0FFFUL << 0)
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#define TD_FRAME_NUM (0x07FFUL << 0)
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#define TD_RESERVED_MASK (0x0FFFUL << 0)
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} __attribute__ ((packed, aligned(4)));
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/* DMA layout of queue heads */
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struct ci_hw_qh {
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/* 0 */
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__le32 cap;
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#define QH_IOS BIT(15)
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#define QH_MAX_PKT (0x07FFUL << 16)
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#define QH_ZLT BIT(29)
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#define QH_MULT (0x0003UL << 30)
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#define QH_ISO_MULT(x) ((x >> 11) & 0x03)
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/* 1 */
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__le32 curr;
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/* 2 - 8 */
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struct ci_hw_td td;
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/* 9 */
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__le32 RESERVED;
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struct usb_ctrlrequest setup;
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} __attribute__ ((packed, aligned(4)));
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struct td_node {
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struct list_head td;
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dma_addr_t dma;
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struct ci_hw_td *ptr;
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int td_remaining_size;
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};
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/**
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* struct ci_hw_req - usb request representation
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* @req: request structure for gadget drivers
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* @queue: link to QH list
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* @tds: link to TD list
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* @sgt: hold original sglist when bounce sglist
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*/
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struct ci_hw_req {
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struct usb_request req;
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struct list_head queue;
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struct list_head tds;
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struct sg_table sgt;
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};
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#ifdef CONFIG_USB_CHIPIDEA_UDC
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int ci_hdrc_gadget_init(struct ci_hdrc *ci);
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void ci_hdrc_gadget_destroy(struct ci_hdrc *ci);
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#else
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static inline int ci_hdrc_gadget_init(struct ci_hdrc *ci)
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{
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return -ENXIO;
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}
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static inline void ci_hdrc_gadget_destroy(struct ci_hdrc *ci)
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{
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}
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#endif
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#endif /* __DRIVERS_USB_CHIPIDEA_UDC_H */
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