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0ffe9eb826
A missing header causes the compiler to warn that the function below is not forward declared. >> drivers/gpu/drm/imagination/pvr_fw_meta.c:33:1: warning: no previous prototype for function 'pvr_meta_cr_read32' [-Wmissing-prototypes] 33 | pvr_meta_cr_read32(struct pvr_device *pvr_dev, u32 reg_addr, u32 *reg_value_out) | ^ drivers/gpu/drm/imagination/pvr_fw_meta.c:32:1: note: declare 'static' if the function is not intended to be used outside of this translation unit 32 | int | ^ | static 1 warning generated. Include the correct header. Reported-by: Arnd Bergmann <arnd@arndb.de> Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202311250226.Da2yiSKp-lkp@intel.com/ Fixes: cc1aeedb98ad ("drm/imagination: Implement firmware infrastructure and META FW support") Signed-off-by: Donald Robson <donald.robson@imgtec.com> Signed-off-by: Maxime Ripard <mripard@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20231130160017.259902-2-donald.robson@imgtec.com
556 lines
16 KiB
C
556 lines
16 KiB
C
// SPDX-License-Identifier: GPL-2.0-only OR MIT
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/* Copyright (c) 2023 Imagination Technologies Ltd. */
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#include "pvr_device.h"
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#include "pvr_fw.h"
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#include "pvr_fw_info.h"
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#include "pvr_fw_meta.h"
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#include "pvr_gem.h"
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#include "pvr_rogue_cr_defs.h"
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#include "pvr_rogue_meta.h"
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#include "pvr_vm.h"
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#include <linux/compiler.h>
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#include <linux/delay.h>
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#include <linux/firmware.h>
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#include <linux/ktime.h>
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#include <linux/types.h>
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#define ROGUE_FW_HEAP_META_SHIFT 25 /* 32 MB */
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#define POLL_TIMEOUT_USEC 1000000
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/**
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* pvr_meta_cr_read32() - Read a META register via the Slave Port
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* @pvr_dev: Device pointer.
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* @reg_addr: Address of register to read.
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* @reg_value_out: Pointer to location to store register value.
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*
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* Returns:
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* * 0 on success, or
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* * Any error returned by pvr_cr_poll_reg32().
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*/
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int
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pvr_meta_cr_read32(struct pvr_device *pvr_dev, u32 reg_addr, u32 *reg_value_out)
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{
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int err;
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/* Wait for Slave Port to be Ready. */
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err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_META_SP_MSLVCTRL1,
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ROGUE_CR_META_SP_MSLVCTRL1_READY_EN |
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ROGUE_CR_META_SP_MSLVCTRL1_GBLPORT_IDLE_EN,
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ROGUE_CR_META_SP_MSLVCTRL1_READY_EN |
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ROGUE_CR_META_SP_MSLVCTRL1_GBLPORT_IDLE_EN,
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POLL_TIMEOUT_USEC);
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if (err)
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return err;
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/* Issue a Read. */
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pvr_cr_write32(pvr_dev, ROGUE_CR_META_SP_MSLVCTRL0,
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reg_addr | ROGUE_CR_META_SP_MSLVCTRL0_RD_EN);
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(void)pvr_cr_read32(pvr_dev, ROGUE_CR_META_SP_MSLVCTRL0); /* Fence write. */
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/* Wait for Slave Port to be Ready. */
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err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_META_SP_MSLVCTRL1,
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ROGUE_CR_META_SP_MSLVCTRL1_READY_EN |
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ROGUE_CR_META_SP_MSLVCTRL1_GBLPORT_IDLE_EN,
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ROGUE_CR_META_SP_MSLVCTRL1_READY_EN |
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ROGUE_CR_META_SP_MSLVCTRL1_GBLPORT_IDLE_EN,
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POLL_TIMEOUT_USEC);
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if (err)
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return err;
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*reg_value_out = pvr_cr_read32(pvr_dev, ROGUE_CR_META_SP_MSLVDATAX);
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return 0;
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}
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static int
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pvr_meta_wrapper_init(struct pvr_device *pvr_dev)
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{
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u64 garten_config;
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/* Configure META to Master boot. */
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pvr_cr_write64(pvr_dev, ROGUE_CR_META_BOOT, ROGUE_CR_META_BOOT_MODE_EN);
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/* Set Garten IDLE to META idle and Set the Garten Wrapper BIF Fence address. */
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/* Garten IDLE bit controlled by META. */
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garten_config = ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_IDLE_CTRL_META;
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/* The fence addr is set during the fw init sequence. */
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/* Set PC = 0 for fences. */
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garten_config &=
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ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_PC_BASE_CLRMSK;
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garten_config |=
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(u64)MMU_CONTEXT_MAPPING_FWPRIV
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<< ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_PC_BASE_SHIFT;
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/* Set SLC DM=META. */
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garten_config |= ((u64)ROGUE_FW_SEGMMU_META_BIFDM_ID)
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<< ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG_FENCE_DM_SHIFT;
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pvr_cr_write64(pvr_dev, ROGUE_CR_MTS_GARTEN_WRAPPER_CONFIG, garten_config);
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return 0;
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}
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static __always_inline void
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add_boot_arg(u32 **boot_conf, u32 param, u32 data)
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{
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*(*boot_conf)++ = param;
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*(*boot_conf)++ = data;
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}
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static int
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meta_ldr_cmd_loadmem(struct drm_device *drm_dev, const u8 *fw,
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struct rogue_meta_ldr_l1_data_blk *l1_data, u32 coremem_size, u8 *fw_code_ptr,
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u8 *fw_data_ptr, u8 *fw_core_code_ptr, u8 *fw_core_data_ptr, const u32 fw_size)
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{
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struct rogue_meta_ldr_l2_data_blk *l2_block =
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(struct rogue_meta_ldr_l2_data_blk *)(fw +
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l1_data->cmd_data[1]);
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struct pvr_device *pvr_dev = to_pvr_device(drm_dev);
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u32 offset = l1_data->cmd_data[0];
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u32 data_size;
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void *write_addr;
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int err;
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/* Verify header is within bounds. */
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if (((u8 *)l2_block - fw) >= fw_size || ((u8 *)(l2_block + 1) - fw) >= fw_size)
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return -EINVAL;
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data_size = l2_block->length - 6 /* L2 Tag length and checksum */;
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/* Verify data is within bounds. */
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if (((u8 *)l2_block->block_data - fw) >= fw_size ||
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((((u8 *)l2_block->block_data) + data_size) - fw) >= fw_size)
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return -EINVAL;
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if (!ROGUE_META_IS_COREMEM_CODE(offset, coremem_size) &&
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!ROGUE_META_IS_COREMEM_DATA(offset, coremem_size)) {
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/* Global range is aliased to local range */
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offset &= ~META_MEM_GLOBAL_RANGE_BIT;
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}
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err = pvr_fw_find_mmu_segment(pvr_dev, offset, data_size, fw_code_ptr, fw_data_ptr,
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fw_core_code_ptr, fw_core_data_ptr, &write_addr);
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if (err) {
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drm_err(drm_dev,
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"Addr 0x%x (size: %d) not found in any firmware segment",
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offset, data_size);
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return err;
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}
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memcpy(write_addr, l2_block->block_data, data_size);
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return 0;
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}
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static int
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meta_ldr_cmd_zeromem(struct drm_device *drm_dev,
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struct rogue_meta_ldr_l1_data_blk *l1_data, u32 coremem_size,
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u8 *fw_code_ptr, u8 *fw_data_ptr, u8 *fw_core_code_ptr, u8 *fw_core_data_ptr)
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{
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struct pvr_device *pvr_dev = to_pvr_device(drm_dev);
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u32 offset = l1_data->cmd_data[0];
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u32 byte_count = l1_data->cmd_data[1];
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void *write_addr;
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int err;
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if (ROGUE_META_IS_COREMEM_DATA(offset, coremem_size)) {
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/* cannot zero coremem directly */
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return 0;
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}
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/* Global range is aliased to local range */
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offset &= ~META_MEM_GLOBAL_RANGE_BIT;
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err = pvr_fw_find_mmu_segment(pvr_dev, offset, byte_count, fw_code_ptr, fw_data_ptr,
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fw_core_code_ptr, fw_core_data_ptr, &write_addr);
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if (err) {
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drm_err(drm_dev,
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"Addr 0x%x (size: %d) not found in any firmware segment",
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offset, byte_count);
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return err;
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}
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memset(write_addr, 0, byte_count);
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return 0;
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}
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static int
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meta_ldr_cmd_config(struct drm_device *drm_dev, const u8 *fw,
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struct rogue_meta_ldr_l1_data_blk *l1_data,
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const u32 fw_size, u32 **boot_conf_ptr)
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{
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struct rogue_meta_ldr_l2_data_blk *l2_block =
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(struct rogue_meta_ldr_l2_data_blk *)(fw +
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l1_data->cmd_data[0]);
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struct rogue_meta_ldr_cfg_blk *config_command;
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u32 l2_block_size;
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u32 curr_block_size = 0;
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u32 *boot_conf = boot_conf_ptr ? *boot_conf_ptr : NULL;
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/* Verify block header is within bounds. */
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if (((u8 *)l2_block - fw) >= fw_size || ((u8 *)(l2_block + 1) - fw) >= fw_size)
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return -EINVAL;
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l2_block_size = l2_block->length - 6 /* L2 Tag length and checksum */;
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config_command = (struct rogue_meta_ldr_cfg_blk *)l2_block->block_data;
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if (((u8 *)config_command - fw) >= fw_size ||
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((((u8 *)config_command) + l2_block_size) - fw) >= fw_size)
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return -EINVAL;
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while (l2_block_size >= 12) {
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if (config_command->type != ROGUE_META_LDR_CFG_WRITE)
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return -EINVAL;
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/*
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* Only write to bootloader if we got a valid pointer to the FW
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* code allocation.
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*/
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if (boot_conf) {
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u32 register_offset = config_command->block_data[0];
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u32 register_value = config_command->block_data[1];
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/* Do register write */
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add_boot_arg(&boot_conf, register_offset,
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register_value);
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}
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curr_block_size = 12;
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l2_block_size -= curr_block_size;
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config_command = (struct rogue_meta_ldr_cfg_blk
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*)((uintptr_t)config_command +
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curr_block_size);
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}
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if (boot_conf_ptr)
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*boot_conf_ptr = boot_conf;
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return 0;
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}
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/**
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* process_ldr_command_stream() - Process LDR firmware image and populate
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* firmware sections
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* @pvr_dev: Device pointer.
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* @fw: Pointer to firmware image.
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* @fw_code_ptr: Pointer to FW code section.
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* @fw_data_ptr: Pointer to FW data section.
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* @fw_core_code_ptr: Pointer to FW coremem code section.
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* @fw_core_data_ptr: Pointer to FW coremem data section.
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* @boot_conf_ptr: Pointer to boot config argument pointer.
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*
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* Returns :
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* * 0 on success, or
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* * -EINVAL on any error in LDR command stream.
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*/
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static int
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process_ldr_command_stream(struct pvr_device *pvr_dev, const u8 *fw, u8 *fw_code_ptr,
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u8 *fw_data_ptr, u8 *fw_core_code_ptr,
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u8 *fw_core_data_ptr, u32 **boot_conf_ptr)
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{
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struct drm_device *drm_dev = from_pvr_device(pvr_dev);
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struct rogue_meta_ldr_block_hdr *ldr_header =
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(struct rogue_meta_ldr_block_hdr *)fw;
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struct rogue_meta_ldr_l1_data_blk *l1_data =
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(struct rogue_meta_ldr_l1_data_blk *)(fw + ldr_header->sl_data);
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const u32 fw_size = pvr_dev->fw_dev.firmware->size;
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int err;
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u32 *boot_conf = boot_conf_ptr ? *boot_conf_ptr : NULL;
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u32 coremem_size;
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err = PVR_FEATURE_VALUE(pvr_dev, meta_coremem_size, &coremem_size);
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if (err)
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return err;
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coremem_size *= SZ_1K;
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while (l1_data) {
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/* Verify block header is within bounds. */
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if (((u8 *)l1_data - fw) >= fw_size || ((u8 *)(l1_data + 1) - fw) >= fw_size)
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return -EINVAL;
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if (ROGUE_META_LDR_BLK_IS_COMMENT(l1_data->cmd)) {
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/* Don't process comment blocks */
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goto next_block;
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}
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switch (l1_data->cmd & ROGUE_META_LDR_CMD_MASK)
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case ROGUE_META_LDR_CMD_LOADMEM: {
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err = meta_ldr_cmd_loadmem(drm_dev, fw, l1_data,
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coremem_size,
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fw_code_ptr, fw_data_ptr,
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fw_core_code_ptr,
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fw_core_data_ptr, fw_size);
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if (err)
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return err;
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break;
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case ROGUE_META_LDR_CMD_START_THREADS:
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/* Don't process this block */
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break;
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case ROGUE_META_LDR_CMD_ZEROMEM:
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err = meta_ldr_cmd_zeromem(drm_dev, l1_data,
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coremem_size,
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fw_code_ptr, fw_data_ptr,
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fw_core_code_ptr,
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fw_core_data_ptr);
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if (err)
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return err;
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break;
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case ROGUE_META_LDR_CMD_CONFIG:
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err = meta_ldr_cmd_config(drm_dev, fw, l1_data, fw_size,
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&boot_conf);
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if (err)
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return err;
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break;
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default:
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return -EINVAL;
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}
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next_block:
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if (l1_data->next == 0xFFFFFFFF)
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break;
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l1_data = (struct rogue_meta_ldr_l1_data_blk *)(fw +
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l1_data->next);
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}
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if (boot_conf_ptr)
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*boot_conf_ptr = boot_conf;
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return 0;
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}
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static void
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configure_seg_id(u64 seg_out_addr, u32 seg_base, u32 seg_limit, u32 seg_id,
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u32 **boot_conf_ptr)
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{
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u32 seg_out_addr0 = seg_out_addr & 0x00000000FFFFFFFFUL;
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u32 seg_out_addr1 = (seg_out_addr >> 32) & 0x00000000FFFFFFFFUL;
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u32 *boot_conf = *boot_conf_ptr;
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/* META segments have a minimum size. */
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u32 limit_off = max(seg_limit, ROGUE_FW_SEGMMU_ALIGN);
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/* The limit is an offset, therefore off = size - 1. */
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limit_off -= 1;
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seg_base |= ROGUE_FW_SEGMMU_ALLTHRS_WRITEABLE;
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add_boot_arg(&boot_conf, META_CR_MMCU_SEGMENT_N_BASE(seg_id), seg_base);
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add_boot_arg(&boot_conf, META_CR_MMCU_SEGMENT_N_LIMIT(seg_id), limit_off);
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add_boot_arg(&boot_conf, META_CR_MMCU_SEGMENT_N_OUTA0(seg_id), seg_out_addr0);
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add_boot_arg(&boot_conf, META_CR_MMCU_SEGMENT_N_OUTA1(seg_id), seg_out_addr1);
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*boot_conf_ptr = boot_conf;
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}
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static u64 get_fw_obj_gpu_addr(struct pvr_fw_object *fw_obj)
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{
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struct pvr_device *pvr_dev = to_pvr_device(gem_from_pvr_gem(fw_obj->gem)->dev);
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struct pvr_fw_device *fw_dev = &pvr_dev->fw_dev;
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return fw_obj->fw_addr_offset + fw_dev->fw_heap_info.gpu_addr;
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}
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static void
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configure_seg_mmu(struct pvr_device *pvr_dev, u32 **boot_conf_ptr)
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{
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const struct pvr_fw_layout_entry *layout_entries = pvr_dev->fw_dev.layout_entries;
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u32 num_layout_entries = pvr_dev->fw_dev.header->layout_entry_num;
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u64 seg_out_addr_top;
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u32 i;
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seg_out_addr_top =
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ROGUE_FW_SEGMMU_OUTADDR_TOP_SLC(MMU_CONTEXT_MAPPING_FWPRIV,
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ROGUE_FW_SEGMMU_META_BIFDM_ID);
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for (i = 0; i < num_layout_entries; i++) {
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/*
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* FW code is using the bootloader segment which is already
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* configured on boot. FW coremem code and data don't use the
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* segment MMU. Only the FW data segment needs to be configured.
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*/
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if (layout_entries[i].type == FW_DATA) {
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u32 seg_id = ROGUE_FW_SEGMMU_DATA_ID;
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u64 seg_out_addr = get_fw_obj_gpu_addr(pvr_dev->fw_dev.mem.data_obj);
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seg_out_addr += layout_entries[i].alloc_offset;
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seg_out_addr |= seg_out_addr_top;
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/* Write the sequence to the bootldr. */
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configure_seg_id(seg_out_addr,
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layout_entries[i].base_addr,
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layout_entries[i].alloc_size, seg_id,
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boot_conf_ptr);
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break;
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}
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}
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}
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static void
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configure_meta_caches(u32 **boot_conf_ptr)
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{
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u32 *boot_conf = *boot_conf_ptr;
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u32 d_cache_t0, i_cache_t0;
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u32 d_cache_t1, i_cache_t1;
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u32 d_cache_t2, i_cache_t2;
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u32 d_cache_t3, i_cache_t3;
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/* Initialise I/Dcache settings */
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d_cache_t0 = META_CR_SYSC_DCPARTX_CACHED_WRITE_ENABLE;
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d_cache_t1 = META_CR_SYSC_DCPARTX_CACHED_WRITE_ENABLE;
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d_cache_t2 = META_CR_SYSC_DCPARTX_CACHED_WRITE_ENABLE;
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d_cache_t3 = META_CR_SYSC_DCPARTX_CACHED_WRITE_ENABLE;
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i_cache_t0 = 0;
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i_cache_t1 = 0;
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i_cache_t2 = 0;
|
|
i_cache_t3 = 0;
|
|
|
|
d_cache_t0 |= META_CR_SYSC_XCPARTX_LOCAL_ADDR_FULL_CACHE;
|
|
i_cache_t0 |= META_CR_SYSC_XCPARTX_LOCAL_ADDR_FULL_CACHE;
|
|
|
|
/* Local region MMU enhanced bypass: WIN-3 mode for code and data caches */
|
|
add_boot_arg(&boot_conf, META_CR_MMCU_LOCAL_EBCTRL,
|
|
META_CR_MMCU_LOCAL_EBCTRL_ICWIN |
|
|
META_CR_MMCU_LOCAL_EBCTRL_DCWIN);
|
|
|
|
/* Data cache partitioning thread 0 to 3 */
|
|
add_boot_arg(&boot_conf, META_CR_SYSC_DCPART(0), d_cache_t0);
|
|
add_boot_arg(&boot_conf, META_CR_SYSC_DCPART(1), d_cache_t1);
|
|
add_boot_arg(&boot_conf, META_CR_SYSC_DCPART(2), d_cache_t2);
|
|
add_boot_arg(&boot_conf, META_CR_SYSC_DCPART(3), d_cache_t3);
|
|
|
|
/* Enable data cache hits */
|
|
add_boot_arg(&boot_conf, META_CR_MMCU_DCACHE_CTRL,
|
|
META_CR_MMCU_XCACHE_CTRL_CACHE_HITS_EN);
|
|
|
|
/* Instruction cache partitioning thread 0 to 3 */
|
|
add_boot_arg(&boot_conf, META_CR_SYSC_ICPART(0), i_cache_t0);
|
|
add_boot_arg(&boot_conf, META_CR_SYSC_ICPART(1), i_cache_t1);
|
|
add_boot_arg(&boot_conf, META_CR_SYSC_ICPART(2), i_cache_t2);
|
|
add_boot_arg(&boot_conf, META_CR_SYSC_ICPART(3), i_cache_t3);
|
|
|
|
/* Enable instruction cache hits */
|
|
add_boot_arg(&boot_conf, META_CR_MMCU_ICACHE_CTRL,
|
|
META_CR_MMCU_XCACHE_CTRL_CACHE_HITS_EN);
|
|
|
|
add_boot_arg(&boot_conf, 0x040000C0, 0);
|
|
|
|
*boot_conf_ptr = boot_conf;
|
|
}
|
|
|
|
static int
|
|
pvr_meta_fw_process(struct pvr_device *pvr_dev, const u8 *fw,
|
|
u8 *fw_code_ptr, u8 *fw_data_ptr, u8 *fw_core_code_ptr, u8 *fw_core_data_ptr,
|
|
u32 core_code_alloc_size)
|
|
{
|
|
struct pvr_fw_device *fw_dev = &pvr_dev->fw_dev;
|
|
u32 *boot_conf;
|
|
int err;
|
|
|
|
boot_conf = ((u32 *)fw_code_ptr) + ROGUE_FW_BOOTLDR_CONF_OFFSET;
|
|
|
|
/* Slave port and JTAG accesses are privileged. */
|
|
add_boot_arg(&boot_conf, META_CR_SYSC_JTAG_THREAD,
|
|
META_CR_SYSC_JTAG_THREAD_PRIV_EN);
|
|
|
|
configure_seg_mmu(pvr_dev, &boot_conf);
|
|
|
|
/* Populate FW sections from LDR image. */
|
|
err = process_ldr_command_stream(pvr_dev, fw, fw_code_ptr, fw_data_ptr, fw_core_code_ptr,
|
|
fw_core_data_ptr, &boot_conf);
|
|
if (err)
|
|
return err;
|
|
|
|
configure_meta_caches(&boot_conf);
|
|
|
|
/* End argument list. */
|
|
add_boot_arg(&boot_conf, 0, 0);
|
|
|
|
if (fw_dev->mem.core_code_obj) {
|
|
u32 core_code_fw_addr;
|
|
|
|
pvr_fw_object_get_fw_addr(fw_dev->mem.core_code_obj, &core_code_fw_addr);
|
|
add_boot_arg(&boot_conf, core_code_fw_addr, core_code_alloc_size);
|
|
} else {
|
|
add_boot_arg(&boot_conf, 0, 0);
|
|
}
|
|
/* None of the cores supported by this driver have META DMA. */
|
|
add_boot_arg(&boot_conf, 0, 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
pvr_meta_init(struct pvr_device *pvr_dev)
|
|
{
|
|
pvr_fw_heap_info_init(pvr_dev, ROGUE_FW_HEAP_META_SHIFT, 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static u32
|
|
pvr_meta_get_fw_addr_with_offset(struct pvr_fw_object *fw_obj, u32 offset)
|
|
{
|
|
u32 fw_addr = fw_obj->fw_addr_offset + offset + ROGUE_FW_SEGMMU_DATA_BASE_ADDRESS;
|
|
|
|
/* META cacheability is determined by address. */
|
|
if (fw_obj->gem->flags & PVR_BO_FW_FLAGS_DEVICE_UNCACHED)
|
|
fw_addr |= ROGUE_FW_SEGMMU_DATA_META_UNCACHED |
|
|
ROGUE_FW_SEGMMU_DATA_VIVT_SLC_UNCACHED;
|
|
|
|
return fw_addr;
|
|
}
|
|
|
|
static int
|
|
pvr_meta_vm_map(struct pvr_device *pvr_dev, struct pvr_fw_object *fw_obj)
|
|
{
|
|
struct pvr_gem_object *pvr_obj = fw_obj->gem;
|
|
|
|
return pvr_vm_map(pvr_dev->kernel_vm_ctx, pvr_obj, 0, fw_obj->fw_mm_node.start,
|
|
pvr_gem_object_size(pvr_obj));
|
|
}
|
|
|
|
static void
|
|
pvr_meta_vm_unmap(struct pvr_device *pvr_dev, struct pvr_fw_object *fw_obj)
|
|
{
|
|
pvr_vm_unmap(pvr_dev->kernel_vm_ctx, fw_obj->fw_mm_node.start,
|
|
fw_obj->fw_mm_node.size);
|
|
}
|
|
|
|
static bool
|
|
pvr_meta_has_fixed_data_addr(void)
|
|
{
|
|
return false;
|
|
}
|
|
|
|
const struct pvr_fw_defs pvr_fw_defs_meta = {
|
|
.init = pvr_meta_init,
|
|
.fw_process = pvr_meta_fw_process,
|
|
.vm_map = pvr_meta_vm_map,
|
|
.vm_unmap = pvr_meta_vm_unmap,
|
|
.get_fw_addr_with_offset = pvr_meta_get_fw_addr_with_offset,
|
|
.wrapper_init = pvr_meta_wrapper_init,
|
|
.has_fixed_data_addr = pvr_meta_has_fixed_data_addr,
|
|
.irq = {
|
|
.enable_reg = ROGUE_CR_META_SP_MSLVIRQENABLE,
|
|
.status_reg = ROGUE_CR_META_SP_MSLVIRQSTATUS,
|
|
.clear_reg = ROGUE_CR_META_SP_MSLVIRQSTATUS,
|
|
.event_mask = ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_EN,
|
|
.clear_mask = ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_CLRMSK,
|
|
},
|
|
};
|